Field of the Invention
The present invention relates in general to entries in a translation address cache of a processor, and more particularly to a system and method of distinguishing system management mode (SMM) entries in the translation address cache for enabling maintenance of non-SMM entries when entering and/or exiting SMM.
Description of the Related Art
Modern processors support virtual memory capability. A virtual memory system maps, or translates, virtual addresses used by a program to physical addresses used by hardware to address memory. Virtual memory has the advantages of hiding the fragmentation of physical memory from the program, facilitating program relocation, and of allowing the program to see a larger memory address space than the actual physical memory available to it. These advantages are particularly beneficial in modern systems that support time-sharing of the processor by multiple programs or processes.
The operating system creates and maintains in memory translation tables, often referred to as page tables in a paged virtual memory system, that map virtual addresses to physical addresses. The translation tables may be in the form of a hierarchy of tables, some of which map virtual addresses to intermediate table addresses. When a program accesses memory using a virtual address, the translation tables are accessed to accomplish the translation of the virtual address to its physical address, commonly referred to as a page table walk, or “tablewalk.” The additional memory accesses to access the translation tables can significantly delay the ultimate access to the memory to obtain the data or instruction desired by the program.
Modern processors include one or more translation address caches to improve performance by addressing the memory access and delay issues. The translation address caches may include a translation-lookaside buffer (TLB). A TLB is a hardware structure of a processor that caches the virtual to physical address translations in order to greatly reduce the likelihood of the need for tablewalks. The virtual address to be translated is compared to previously stored virtual addresses in the TLB and if the virtual address hits in the TLB (e.g., when a virtual address match is found), the TLB provides the physical address. Retrieving the physical address from the TLB consumes much less time than would be required to access the translation tables in memory to perform the tablewalk. The efficiency (hit rate) of TLBs is crucial to processor performance.
The translation address caches may also include a paging structure cache that caches information for one or more of the page tables. For example, some paging modes may use a level 4 page map table (PML4), a page directory pointer table (PDPT), a page directory (PD), and a page table (PT), in which a paging cache may be provided for one or more of these page tables. The paging structure cache incorporates any one or more of these paging caches. In this manner, even if there is a miss in the TLB, the tablewalk process may be significantly accelerated if the requested address translation is cached within the paging structure cache.
Modern processors and processing systems support a system management mode (SMM) in which normal processing is interrupted and suspended. SMM operation is entered in response to an external stimulus, such as an SMM interrupt (SMI). SMM operation is usually temporary in which normal processing may be resumed at the point in which normal processing was interrupted. SMM is particularly advantageous for entering any one or more low power modes to conserve power. The processor enters the SMM in response to the assertion of an SMM interrupt. Prior to entering SMM, the processor microcode saves the state of the processor in an SMM save area and puts the processor into a known state. The known state may be considered an isolated operating mode in order to perform one or more valuable functions separate from normal operating mode, such as performing power saving functions or the like. When it is desired to return to the normal operating mode, a resume (RSM) instruction is executed to exit SMM. In the process of exiting SMM, the microcode restores the saved state from the SMM save area and takes the processor back to the operating mode that existed prior to the SMI.
In the conventional configuration, most, if not all of the cached address translations are flushed as the processor enters and/or exits SMM. The flushing of the cached information was performed to ensure proper operation when normal operation is resumed since SMM is considered a separate operating mode using a different address space. A hit within a translation address cache (e.g., TLB or paging structure cache) during normal mode with an SMM entry causes a false hit, which in turn may result in improper operation or even system failure.